Flash memory is a type of electronic memory media that can hold its data in the absence of operating power. Flash memory can be programmed, erased, and reprogrammed during its useful life (which may be up to one million write cycles for typical flash memory devices). Flash memory is becoming increasingly popular as a reliable, compact, and inexpensive nonvolatile memory in a number of consumer, commercial, and other applications. As electronic devices get smaller and smaller, it becomes desirable to increase the amount of data that can be stored per unit area on an integrated circuit memory cell, such as a flash memory unit.
One conventional flash memory technology is based upon a memory cell that utilizes a charge trapping dielectric cell that is capable of storing two bits of data. One example of this type of non-volatile memory device is known as a dual-bit Flash electrically erasable and programmable read-only memory (EEPROM), which is available under the trademark MIRRORBIT™ from Spansion, Inc., Sunnyvale, Calif. Such dual-bit memory cells utilize a single silicon nitride layer having two separate charge storage regions to store charge within the silicon nitride layer. In such an arrangement, one bit can be stored using a first charge storing region on one side of the silicon nitride layer, while a second bit can be stored using a second charge storing region on the other side of the same silicon nitride layer. For example, a left bit and right bit can be stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell, respectively. In comparison to a conventional EEPROM cell, a dual-bit memory cell can store twice as much information in a memory array of equal size.
FIG. 1 is a cross-sectional view of a conventional dual-bit memory cell 50. The memory cell 50 has a dual-bit (bit1, bit2) architecture that allows twice as much storage capacity as a conventional EEPROM memory device.
The conventional memory cell 50 includes a substrate 54, a first insulator layer 62 disposed over the substrate 54, a nitride charge storage layer 64 disposed over the first insulator layer 62, a second insulator layer 66 disposed over the charge storage layer 64, and a polysilicon control gate 68 disposed over the second insulator layer 66. To produce an operable memory device, a first metal silicide contact (not shown) can be disposed on substrate 54, and the control gate 66 can be capped with a second metal silicide contact (not shown).
In one implementation, the substrate 54 is a P-type semiconductor substrate 54 having a first buried junction region 60 and a second buried junction region 61 formed within substrate 54 in self-alignment with the memory cell 50. First buried junction region 60 and second buried junction region 61 are each formed from an N+ semiconductor material. The first insulator layer 62, the charge storage layer 64, and the second insulator layer 66 can be implemented using an oxide-nitride-oxide (ONO) configuration in which a nitride charge storage layer 64 is sandwiched between two silicon dioxide insulator layers 62, 66. Alternatively, charge storage layer 64 may utilize buried polysilicon islands as a charge trapping layer. The charge storage layer 64 is capable of holding a charge.
Memory cell 50 can store two data bits: a left bit represented by the circle (bit 1); and a right bit represented by the circle (bit 2). In practice, memory cell 50 is generally symmetrical, thus first buried junction region 60 and second buried junction region 61 are interchangeable. In this regard, first buried junction region 60 may serve as the source region with respect to the right bit (bit 2), while second buried junction region 61 may serve as the drain region with respect to the right bit (bit 2). Conversely, second buried junction region 61 may serve as the source region with respect to the left bit (bit 1), while first buried junction region 60 may serve as the drain region with respect to the left bit (bit 1).
While a single dual-bit memory cell 50 is illustrated in FIG. 1, it will be appreciated that any suitable number of the dual-bit memory cells 50 could be used to form a memory array, as described below with reference to FIG. 2.
FIG. 2 is a simplified diagram of a plurality of dual-bit memory cells arranged in accordance with a conventional array architecture 200 (a practical array architecture can include thousands of dual-bit memory cells 50). Array architecture 200 includes a number of buried bit lines formed in a semiconductor substrate as mentioned above. FIG. 2 depicts three buried bit lines (BLs) 202, 204, and 206, each being capable of functioning as a drain or a source for memory cells in array architecture 200. Array architecture 200 also includes a number of word lines (WLs) correspond to the gate of the memory cells and are utilized to control the gate voltage of the memory cells. FIG. 2 depicts four WLs 208, 210, 212, and 214 that generally form a crisscross pattern with the bit lines. Although not shown in FIG. 2, charge storage layer, such as an ONO stack, resides between the BLs and the WLs. The dashed lines in FIG. 2 represent two of the dual-bit memory cells in array architecture 200: a first cell 216 and a second cell 218. Notably, BL 204 is shared by first cell 216 and second cell 218. Array architecture 200 is known as a virtual ground architecture because ground potential can be applied to any selected BL and there need not be any BLs with a fixed ground potential.
Control logic and circuitry (not shown) for array architecture 200 governs the selection of memory cells, the application of voltage to the WLs 208, 210, 212, 214, and the application of voltage to the BLs 202, 204, 206 during conventional flash memory operations, such as: programming; reading; erasing; and soft programming. Voltage is delivered to the BLs 202, 204, 206 using BL contacts 230. FIG. 2 depicts three conductive metal lines 220, 222, and 224 and three BL contacts 226, 228, and 230. Because the resistance of the BLs 202, 204, 206 is very high, for a given BL 202, 204, 206, a BL contact is used, for example, once every 8, 16, or 256 WLs.
Referring again to FIG. 1, a memory cell can be programmed using hot electron injection techniques (also known as channel hot electron or CHE programming). In accordance with conventional programming techniques, the right bit 64 is programmed by applying a relatively high programming voltage to gate 68 via the appropriately selected WL, grounding the BL corresponding to first buried junction region 60 (which serves as the source in this case), and applying a relatively high drain bias voltage to the BL corresponding to second buried junction region 61 (which serves as the drain in this case). Conversely, the right bit 64 is programmed by applying a relatively high programming voltage to gate 68 via the appropriately selected WL, grounding the BL corresponding to second buried junction region 61 (which serves as the source in this case), and applying a relatively high drain bias voltage to the BL corresponding to first buried junction region 60 (which serves as the drain in this case).
Referring again to FIG. 2, conventional CHE programming of a flash memory array arranged in a virtual ground architecture may result in undesired BL to BL leakage current flowing under the unselected WLs, between the WLs, and in the BL contact areas. This BL to BL leakage current become increasingly worse as the cell size shrinks. Such BL leakage current can increase the required programming current. Moreover, the amount of this parasitic leakage current can be further increased due to natural degradation of the cells after the array has experienced many program-erase cycles. Excessive leakage current can be very undesirable in low power applications such as portable electronic devices, wireless telephones, or the like. Excessive leakage current may have other negative implications in a practical flash memory device. BL leakage current can also occur during conventional read and verification operations for virtual ground architecture (e.g., verification operations such as soft program verify, erase verify, and program verify) and adversely affect the read and verification results. Accordingly, it is desirable to control, reduce, or eliminate leakage current during programming of memory cells in a virtual ground architecture. In addition, it is desirable to control, reduce, or eliminate the leakage current component during read and verification operations of memory cells in a virtual ground architecture.
FIG. 3 is a simplified top view of a portion of a conventional array architecture 300 including a plurality of dual-bit memory cells. The array 300 has a “virtual ground layout” and comprises a plurality of bit lines 301-305, a plurality of word lines 308-372, and a plurality of bit line contacts 380-395. In the areas of the array 300 above the bit line contacts 380-395, there are no word lines present.
As noted above, it is desirable to control, reduce or eliminate BL-to-BL leakage currents (IL). For instance, in the areas under the WLs 308-372, unwanted BL-to-BL leakage current (IL) can be effectively controlled by applying appropriate bias voltage to the WLs 308-372. In addition, in the areas between adjacent or neighboring WLs 308-372, WL-to-WL leakage currents can also be controlled or shut off by the fringing field from the WLs 308-372 since the WL-to-WL distance is also very small. In other words, the fringing fields between the closely packed WLs 308-372 can also be used to control leakage currents between the WLs 308-372.
However, in the vicinity of the bit line contact areas 380-395 there are no WLs 308-370 which cover the bit line contact areas 380-395. The space occupied by the bit line contact areas 380-395 is relatively large in comparison to the dimensions of the WLs 308-370 and/or the spacings between the WLs 308-370. As such, in the regions 399 between the bit line contacts 380-395, leakage currents (IL) can flow between adjacent or neighboring bit lines 301-305. Bit line leakage currents can also be problematic at the end of the array 300 where there are bit line contacts (not shown) which do not have corresponding WLs in the vicinity.
FIG. 4 is a simplified cross-sectional view of FIG. 3 taken along the line X-X′ in FIG. 3. The cross-section 400 includes a substrate 354, buried bit lines 301, 302; spacers 372, insulator regions 374, and a plurality of bit line contacts 380, 382. The insulator regions 374 may comprise an insulator material such as an oxide or other insulator layer. For instance, the insulator regions 374 can be fabricated using a high density plasma (HDP) deposition technique to deposit an oxide on top of the bit lines 301, 302.
As memory cell size in the dual-bit memory device is scaled smaller (e.g., continues to shrink), the bit lines 301-305 are packed closer and closer together. As such, leakage current (IL) issues become worse since the BL-to-BL distance separation decreases. Because WLs are not present in the vicinity of the BL contacts 380, 382, this makes it difficult to suppress leakage current (IL) in the vicinity of the BL contacts 380, 382. For instance, the bit lines 301, 302 are susceptible to a leakage current (IL) flowing between the adjacent or neighboring bit lines 301, 302.
Notwithstanding these advances, it would be desirable to provide improved techniques for reducing or preventing BL-to-BL leakage current in the BL contact area of a dual-bit memory cell. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.